The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to a method of manufacturing a semiconductor device which has a step for forming electrodes and wiring strips, using self-aligned contact holes.
Recent advances in techniques for manufacturing semiconductor devices and particularly semiconductor integrated circuits are significant. Improvements are particularly seen in photolithography, ion implantation, dry etching and so on. However, even if elements are micronized by these techniques, the packaging density is limited due to various restrictions in forming contact holes, positioning margin and in the like process.
In view of this, a self-aligned contact (S.A.C.) technique is known as a method for forming a contact hole in self-alignment with a gate electrode in the manufacture of a MOS transistor. Such S.A.C. technique entitled as SELOCS (selective oxide coating of silicon gates) is published by HIDEO SUNAMI in Japanese Journal of Applied Physics, Vol. 18 (1979), pp. 255 to 260. According to this technique, a phosphorus-doped polycrystalline silicon (polysilicon) pattern having a high impurity concentration is formed on a gate oxide film which is formed on a p-type single crystal silicon substrate, and the polysilicon pattern thus formed is used as a gate electrode. Thermal oxidation is then performed to form a thick oxide film around the gate electrode and a thin oxide film on the exposed surface of the substrate. This is achieved because the oxidation rate of the phosphorus-doped polysilicon is greater than that of single crystal silicon. Thereafter, the oxide films are etched. The thin oxide film on the surface (source and drain) of the substrate is etched to expose the surface of the substrate, but the thick oxide film around the gate electrode partially remains. The exposed surface portion of the substrate is used as source and drain contact holes. The distances between the source and gate electrode and between the drain and gate electrode may therefore be minimized without requiring margins for positioning.
However, this SELCOS method has various problems to be described below.
The first problem is a low breakdown voltage of the thick oxide film around the gate electrode. In general, an oxide film which is obtained by etching has more enhanced defects and has greater characteristic variations than an epitaxially grown SiO.sub.2 film. In particular, polysilicon doped with a high concentration of an impurity has a large crystal grain size and tends to have holes due to crystal interfaces or pinholes due to the photolithography process. For this reason, an oxide film obtained by thermally oxidizing a gate electrode made of such polysilicon of a high impurity concentration has poor characteristics. When such an oxide film is etched, a breakdown voltage (gate breakdown voltage, and breakdown voltage between the gate and source or between the source and drain) may be lowered.
The second problem is an undesirable increase in the parasitic capacitance between the gate electrode and source or drain. This is attributed to the small thickness of the oxide film around the gate electrode, the small distance between the gate electrode and the source or drain electrodes, and the large opposing areas of these electrodes. Although this problem may be partially solved by circuit design or the like, this imposes further limitations on circuit design.
The third problem is variations in the characteristics (fluctuations in the threshold voltage Vth). The difference in the oxidation rate of polysilicon and single crystal silicon by wet oxidation is reversely proportional to the oxidation temperature. However, an oxide film formed by wet oxidation at a low temperature has poor characteristics. Furthermore, the above-mentioned difference in oxidation rate increases with an increase in the concentration of the impurity in polysilicon. However, if the polysilicon of the gate electrode has a high impurity concentration, the impurity in the polysilicon is activated and diffused into the oxide film formed on the exposed surface of the single crystal silicon substrate. The impurity is further diffused from the oxide film into the substrate, causing further variations in the threshold voltage Vth.
The fourth problem is as follows. When the oxide film around the gate electrode of polysilicon is made thicker for improved breakdown voltage, that is, when the thermal oxidation time is prolonged, the above-mentioned difference in the oxidation rate is reduced. Then, contact holes for source and drain may not be formed in self-alignment with the gate electrode.
The fifth problem is that when a thick oxide film is formed around the gate electrode of polysilicon, the gate electrode is narrowed. Especially when the gate electrode has a step portion, disconnection may be caused at such a step portion. This is because it is very difficult to control the oxidation conditions and optimal setting of the impurity concentration in the polysilicon. When the gate electrode is micronized, the narrow gate electrode results in an increase in resistance and thus impairs high-speed and high-performance operation of the MOS transistor.
The sixth problem is that micronization of a MOS transistor (semiconductor device) is limited since a positioning margin must be allowed between the source and drain electrodes. Since the source and drain electrodes overlap the oxide film on the gate electrode, a positioning marging (e.g., 1 to 2 .mu.m) must be allowed between these electrodes if the electrodes are to be formed by photolithography. Therefore, if the MOS transistor is micronized, for example, with gate electrode width set to 1.0 .mu.m, the source and drain electrodes cannot be formed with good precision unless the positioning margin is reduced to zero. However, it is practically impossible to reduce the margin to zero. Thus, although the SELCOS method is an excellent micronization technique which allows opening of contact holes in self-alignment with a gate electrode, it may not be effectively utilized. Furthermore, since the source and drain electrodes overlap the oxide film on the gate electrode, the parasitic capacitance increases between the overlapping portions of the gate electrode and the source and drain electrodes. This degrades performance of the MOS transistor.
Meanwhile, a method is proposed for forming a micronized gate electrode of a refractory metal silicide in the manufacture of a MOS transistor. Such a method is disclosed in Shinji Okazaki et al. "Edge-Defined Patterning of Hyperfine Refractory Metal Silicide MOS Structures" in IEEE TRANSACTION OF ELECTRON DEVICES, VOL. ED-28, NO-11, November 1981, pp. 1364 to 1368. In this method, as shown in FIGS. 1A to 1D, a vertical edge is formed on oxide film which is formed on a silicon substrate through. A gate material (e.g., MOSi.sub.2) is deposited and covers the vertical edge. The gate material is selectively etched by anisotropic etching to leave the gate material on the vertical edge and to form a gate electrode having hyperfine dimensions (&lt;1/4 .mu.m). The vertical edge is then etched, and the exposed oxide film is selectively etched. Thus, in accordance with this method, the gate material left on the vertical edge is used to form a gate electrode having hyperfine dimensions.